The present invention relates to a method for selectively forming a conductive material, and particularly to a method of forming multilevel interconnections for a semiconductor device. More particularly, the present invention relates to a method for forming via plugs within vila hiles which electrically connects a lower layer wiring to an upper layer wiring in a multilevel interconnect structure.
Current requirements for high speed operation in computer systems have demanded greater improvements in the high-level integration and high-speed operation of a semiconductor integrated circuits. Therefore, both the microminiaturization of semiconductor devices, and the microminiaturization and multilayered structure of wirings are considered more and more important.
In order to realize such multilevel interconnect structures, developments in the techniques for planarizing interlevel dielectric films and in the techniques for forming wirings in fine miniaturized holes used in connecting layers of multilevel interconnect structures are particularly important. Greater reliability in multilevel interconnections may be improved by perfecting such techniques.
Some planarization methods for the interlevel dielectric film formation of conventional multilevel interconnect structures include the organic resin coating method, SOG (spin on glass) coating method, etchback method and bias sputterizing method. Among these methods, the planarization method by coating an organic resin is a very simple process, and, has superior planarization characteristics.
For forming multilevel interconnections, plugs are formed by filling fine via holes formed on the interlevel dielectric film with conductive material. Usually, the selective CVD (Chemical Vapor Deposition) method with tungsten (W) using tungsten hexafluoride (WF.sub.6) as the source gas and hydrogen (H.sub.2) or silane (SiH.sub.4) as the reduction agent has been used to form such plugs. This method has been described, for example, in the reference IEEE IEDM Technical Digest (1987) by T. Ohba, S. Inoue and M. Maeda.
Tungsten (W) deposited on the bottom of the via holes forms well on exposed conductor surfaces such as metal, but W is difficult to deposit on inorganic dielectric films. This is referred to as when the deposition of W has "good selectivity". Enhancing the reliability of multilevel interconnections requires "good selectivity". For this purpose, PSG (Phosphor Silicate Glass) films or silicon dioxide (SiO.sub.2) films formed through the thermal CVD method are excellent inorganic dielectric films. However, good selectivity cannot be obtained with SiO.sub.2 films and silicon nitride (Si.sub.3 N.sub.4) films which are formed using either a sputtering method and plasma CVD method.
It has been assumed that a desired via plug for via hole can be attained when selective CVD of tungsten W is performed on SiO.sub.2 film or PSG formed by thermal CVD on an organic resin film coated for planarization. However, the SiO.sub.2 film and PSG formed by the thermal CVD method on the organic resin film have inferior adhesion properties compared to organic resin films and have weak mechanical strength. As a result, the reliability of the wiring is lower because peeling and/or cracks can occur in the course of the manufacturing process.
Recently, however, it has been disclosed by the Japanese Laid-open Patent No. 77131/1989 (by Fukuyama, et al) that a planar dielectric film ensuring good adhesion may be obtained by forming an inorganic dielectric film on the planarized resin film using an ion beam assisted deposition method. However, as explained above, assuming from the fact that CVD having good selectivity cannot be obtained for the SiO.sub.2 film or Si.sub.3 N.sub.4 film formed by the sputtering method of plasma CVD method, it has been thought that CVD having good selectivity also cannot be obtained for the SiO.sub.2 film or Si.sub.3 N.sub.4 film formed using the ion beam assisted deposition method.